; Generated by PSoC Designer ???
;
; CSDCapacitor address and mask equates
CSDCapacitor_Data_ADDR:	equ	0h
CSDCapacitor_DriveMode_0_ADDR:	equ	100h
CSDCapacitor_DriveMode_1_ADDR:	equ	101h
CSDCapacitor_DriveMode_2_ADDR:	equ	3h
CSDCapacitor_GlobalSelect_ADDR:	equ	2h
CSDCapacitor_IntCtrl_0_ADDR:	equ	102h
CSDCapacitor_IntCtrl_1_ADDR:	equ	103h
CSDCapacitor_IntEn_ADDR:	equ	1h
CSDCapacitor_MASK:	equ	80h
CSDCapacitor_MUXBusCtrl_ADDR:	equ	1d8h
; CSDSW0 address and mask equates
CSDSW0_Data_ADDR:	equ	10h
CSDSW0_DriveMode_0_ADDR:	equ	110h
CSDSW0_DriveMode_1_ADDR:	equ	111h
CSDSW0_DriveMode_2_ADDR:	equ	13h
CSDSW0_GlobalSelect_ADDR:	equ	12h
CSDSW0_IntCtrl_0_ADDR:	equ	112h
CSDSW0_IntCtrl_1_ADDR:	equ	113h
CSDSW0_IntEn_ADDR:	equ	11h
CSDSW0_MASK:	equ	2h
CSDSW0_MUXBusCtrl_ADDR:	equ	1ech
; CSDSW0_Data access macros
;   GetCSDSW0_Data macro, return in a
macro GetCSDSW0_Data
	mov		a,[Port_4_Data_SHADE]
	and		a, 2h
endm
;   SetCSDSW0_Data macro
macro SetCSDSW0_Data
	or		[Port_4_Data_SHADE], 2h
	mov		a, [Port_4_Data_SHADE]
	mov		reg[CSDSW0_Data_ADDR], a
endm
;   ClearCSDSW0_Data macro
macro ClearCSDSW0_Data
	and		[Port_4_Data_SHADE], ~2h
	mov		a, [Port_4_Data_SHADE]
	mov		reg[CSDSW0_Data_ADDR], a
endm

; CSDSW1 address and mask equates
CSDSW1_Data_ADDR:	equ	10h
CSDSW1_DriveMode_0_ADDR:	equ	110h
CSDSW1_DriveMode_1_ADDR:	equ	111h
CSDSW1_DriveMode_2_ADDR:	equ	13h
CSDSW1_GlobalSelect_ADDR:	equ	12h
CSDSW1_IntCtrl_0_ADDR:	equ	112h
CSDSW1_IntCtrl_1_ADDR:	equ	113h
CSDSW1_IntEn_ADDR:	equ	11h
CSDSW1_MASK:	equ	8h
CSDSW1_MUXBusCtrl_ADDR:	equ	1ech
; CSDSW1_Data access macros
;   GetCSDSW1_Data macro, return in a
macro GetCSDSW1_Data
	mov		a,[Port_4_Data_SHADE]
	and		a, 8h
endm
;   SetCSDSW1_Data macro
macro SetCSDSW1_Data
	or		[Port_4_Data_SHADE], 8h
	mov		a, [Port_4_Data_SHADE]
	mov		reg[CSDSW1_Data_ADDR], a
endm
;   ClearCSDSW1_Data macro
macro ClearCSDSW1_Data
	and		[Port_4_Data_SHADE], ~8h
	mov		a, [Port_4_Data_SHADE]
	mov		reg[CSDSW1_Data_ADDR], a
endm

; CSDSW2 address and mask equates
CSDSW2_Data_ADDR:	equ	10h
CSDSW2_DriveMode_0_ADDR:	equ	110h
CSDSW2_DriveMode_1_ADDR:	equ	111h
CSDSW2_DriveMode_2_ADDR:	equ	13h
CSDSW2_GlobalSelect_ADDR:	equ	12h
CSDSW2_IntCtrl_0_ADDR:	equ	112h
CSDSW2_IntCtrl_1_ADDR:	equ	113h
CSDSW2_IntEn_ADDR:	equ	11h
CSDSW2_MASK:	equ	20h
CSDSW2_MUXBusCtrl_ADDR:	equ	1ech
; CSDSW2_Data access macros
;   GetCSDSW2_Data macro, return in a
macro GetCSDSW2_Data
	mov		a,[Port_4_Data_SHADE]
	and		a, 20h
endm
;   SetCSDSW2_Data macro
macro SetCSDSW2_Data
	or		[Port_4_Data_SHADE], 20h
	mov		a, [Port_4_Data_SHADE]
	mov		reg[CSDSW2_Data_ADDR], a
endm
;   ClearCSDSW2_Data macro
macro ClearCSDSW2_Data
	and		[Port_4_Data_SHADE], ~20h
	mov		a, [Port_4_Data_SHADE]
	mov		reg[CSDSW2_Data_ADDR], a
endm

; CSDSW3 address and mask equates
CSDSW3_Data_ADDR:	equ	10h
CSDSW3_DriveMode_0_ADDR:	equ	110h
CSDSW3_DriveMode_1_ADDR:	equ	111h
CSDSW3_DriveMode_2_ADDR:	equ	13h
CSDSW3_GlobalSelect_ADDR:	equ	12h
CSDSW3_IntCtrl_0_ADDR:	equ	112h
CSDSW3_IntCtrl_1_ADDR:	equ	113h
CSDSW3_IntEn_ADDR:	equ	11h
CSDSW3_MASK:	equ	80h
CSDSW3_MUXBusCtrl_ADDR:	equ	1ech
; CSDSW3_Data access macros
;   GetCSDSW3_Data macro, return in a
macro GetCSDSW3_Data
	mov		a,[Port_4_Data_SHADE]
	and		a, 80h
endm
;   SetCSDSW3_Data macro
macro SetCSDSW3_Data
	or		[Port_4_Data_SHADE], 80h
	mov		a, [Port_4_Data_SHADE]
	mov		reg[CSDSW3_Data_ADDR], a
endm
;   ClearCSDSW3_Data macro
macro ClearCSDSW3_Data
	and		[Port_4_Data_SHADE], ~80h
	mov		a, [Port_4_Data_SHADE]
	mov		reg[CSDSW3_Data_ADDR], a
endm

; CSDResistor address and mask equates
CSDResistor_Data_ADDR:	equ	14h
CSDResistor_DriveMode_0_ADDR:	equ	114h
CSDResistor_DriveMode_1_ADDR:	equ	115h
CSDResistor_DriveMode_2_ADDR:	equ	17h
CSDResistor_GlobalSelect_ADDR:	equ	16h
CSDResistor_IntCtrl_0_ADDR:	equ	116h
CSDResistor_IntCtrl_1_ADDR:	equ	117h
CSDResistor_IntEn_ADDR:	equ	17h
CSDResistor_MASK:	equ	20h
CSDResistor_MUXBusCtrl_ADDR:	equ	1edh
