; Generated by PSoC Designer ???
;
;=============================================================================
;  FILENAME:   GlobalParams.inc
;  DATE:       27 September 2004
;
;  DESCRIPTION:
;  Constants describing many of the global parameter settings.
;  This file contains equates to support oscillator register initialization
;  for the CY8C24894
;
;  Copyright (C) Cypress MicroSystems 2000-2004. All rights reserved.
;
; NOTES:
; Do not modify this file. It is generated by PSoC Designer each time the
; generate application function is run. The values of the parameters in this
; file can be modified by changing the values of the global parameters in the
; device editor.
;=============================================================================
;

CPU_CLOCK:				equ	2h	;CPU clock value
CPU_CLOCK_MASK:			equ	7h	;CPU clock mask
CPU_CLOCK_JUST:			equ	2h	;CPU clock value justified
SLEEP_TIMER:			equ	1h	;Sleep Timer value
SLEEP_TIMER_MASK:		equ	18h	;Sleep Timer mask
SLEEP_TIMER_JUST:		equ	8h	;Sleep Timer value justified
LVD_TBEN:               equ 0   ; Low Voltage Throttle-back enable value
LVD_TBEN_MASK:          equ 8  ; Low Voltage Throttle-back enable mask
LVD_TBEN_JUST:          equ 0  ; Low Voltage Throttle-back enable justified
TRIP_VOLTAGE:			equ	2h   ;Trip Voltage value
TRIP_VOLTAGE_MASK:      equ 7h  ;Trip Voltage mask
TRIP_VOLTAGE_JUST:      equ 2h  ;Trip Voltage justified
                              
POWER_SETTING:			equ	8h
POWER_SET_5V0:          equ 10h  ; MASK for 5.0V operation, fast and slow 
POWER_SET_5V0_24MHZ:    equ 10h  ; Power Setting value for 5.0V fast      
POWER_SET_3V3:          equ 08h  ; MASK for 3.3V operation, fast and slow 
POWER_SET_3V3_24MHZ:    equ 08h	 ; Power Setting value for 3.3V fast      

COMM_RX_PRESENT:		equ	0	;1 = TRUE
WATCHDOG_ENABLE:		equ 0	;Watchdog Enable 1 = Enable

CLOCK_DIV_VC1:			equ	0h	;VC1 clock divider
CLOCK_DIV_VC1_MASK:		equ	f0h	;VC1 clock divider mask
CLOCK_DIV_VC1_JUST:		equ	0h	;VC1 clock divider justified
CLOCK_DIV_VC2:			equ	0h	;VC2 clock divider
CLOCK_DIV_VC2_MASK:		equ	fh	;VC2 clock divider mask
CLOCK_DIV_VC2_JUST:		equ	0h	;VC2 clock divider justified
CLOCK_INPUT_VC3:		equ	0h	;VC3 clock source
CLOCK_INPUT_VC3_MASK:	equ	3h	;VC3 clock source mask
CLOCK_INPUT_VC3_JUST:	equ	0h	;VC3 clock source justified
CLOCK_DIV_VC3:			equ	0h	;VC3 clock divider
CLOCK_DIV_VC3_MASK:		equ	ffh	;VC3 clock divider mask
CLOCK_DIV_VC3_JUST:		equ	0h	;VC3 clock divider justified
ANALOG_BUFFER_PWR:		equ	0h	;Analog buffer power level
ANALOG_BUFFER_PWR_MASK:	equ	1h	;Analog buffer power level mask
ANALOG_BUFFER_PWR_JUST:	equ	0h	;Analog buffer power level justified
ANALOG_POWER:			equ	1h	;Analog power control
ANALOG_POWER_MASK:		equ	7h	;Analog power control mask
ANALOG_POWER_JUST:		equ	1h	;Analog power control justified
OP_AMP_BIAS:			equ	0h	;Op amp bias level
OP_AMP_BIAS_MASK:		equ	40h	;Op amp bias level mask
OP_AMP_BIAS_JUST:		equ	0h	;Op amp bias level justified
REF_MUX:				equ	0h	;Ref mux setting
REF_MUX_MASK:			equ	38h	;Ref mux setting mask
REF_MUX_JUST:			equ	0h	;Ref mux setting justified
AGND_BYPASS:			equ	0h	;AGndBypass setting
AGND_BYPASS_MASK:		equ	40h	;AGndBypass setting mask
AGND_BYPASS_JUST:		equ	0h	;AGndBypass setting justified
SYSCLK_SOURCE:				equ	(0h | 0h)	;SysClk Source setting
SYSCLK_SOURCE_MASK:			equ	(4h | 2h)	;SysClk Source setting mask
SYSCLK_SOURCE_JUST:			equ	(0h | 0h)	;SysClk Source setting justified
SYSCLK_2_DISABLE:				equ	0h	;SysClk*2 Disable setting
SYSCLK_2_DISABLE_MASK:			equ	1h	;SysClk*2 Disable setting mask
SYSCLK_2_DISABLE_JUST:			equ	0h	;SysClk*2 Disable setting justified
;
; register initial values
;
ANALOG_IO_CONTROL:		equ 0h	;Analog IO Control register (ABF_CR)
PORT_0_GLOBAL_SELECT:	equ 0h	;Port 0 global select register (PRT0GS)
PORT_0_DRIVE_0:			equ 0h	;Port 0 drive mode 0 register (PRT0DM0)
PORT_0_DRIVE_1:			equ ffh	;Port 0 drive mode 1 register (PRT0DM1)
PORT_0_DRIVE_2:			equ ffh	;Port 0 drive mode 2 register (PRT0DM2)
PORT_0_INTENABLE:		equ 0h	;Port 0 interrupt enable register (PRT0IE)
PORT_0_INTCTRL_0:		equ 0h	;Port 0 interrupt control 0 register (PRT0IC0)
PORT_0_INTCTRL_1:		equ 0h	;Port 0 interrupt control 1 register (PRT0IC1)
PORT_1_GLOBAL_SELECT:	equ 0h	;Port 1 global select register (PRT1GS)
PORT_1_DRIVE_0:			equ 0h	;Port 1 drive mode 0 register (PRT1DM0)
PORT_1_DRIVE_1:			equ ffh	;Port 1 drive mode 1 register (PRT1DM1)
PORT_1_DRIVE_2:			equ ffh	;Port 1 drive mode 2 register (PRT1DM2)
PORT_1_INTENABLE:		equ 0h	;Port 1 interrupt enable register (PRT1IE)
PORT_1_INTCTRL_0:		equ 0h	;Port 1 interrupt control 0 register (PRT1IC0)
PORT_1_INTCTRL_1:		equ 0h	;Port 1 interrupt control 1 register (PRT1IC1)
PORT_2_GLOBAL_SELECT:	equ 0h	;Port 2 global select register (PRT2GS)
PORT_2_DRIVE_0:			equ 0h	;Port 2 drive mode 0 register (PRT2DM0)
PORT_2_DRIVE_1:			equ ffh	;Port 2 drive mode 1 register (PRT2DM1)
PORT_2_DRIVE_2:			equ ffh	;Port 2 drive mode 2 register (PRT2DM2)
PORT_2_INTENABLE:		equ 0h	;Port 2 interrupt enable register (PRT2IE)
PORT_2_INTCTRL_0:		equ 0h	;Port 2 interrupt control 0 register (PRT2IC0)
PORT_2_INTCTRL_1:		equ 0h	;Port 2 interrupt control 1 register (PRT2IC1)
PORT_3_GLOBAL_SELECT:	equ 0h	;Port 3 global select register (PRT3GS)
PORT_3_DRIVE_0:			equ 0h	;Port 3 drive mode 0 register (PRT3DM0)
PORT_3_DRIVE_1:			equ bfh	;Port 3 drive mode 1 register (PRT3DM1)
PORT_3_DRIVE_2:			equ bfh	;Port 3 drive mode 2 register (PRT3DM2)
PORT_3_INTENABLE:		equ 0h	;Port 3 interrupt enable register (PRT3IE)
PORT_3_INTCTRL_0:		equ 0h	;Port 3 interrupt control 0 register (PRT3IC0)
PORT_3_INTCTRL_1:		equ 0h	;Port 3 interrupt control 1 register (PRT3IC1)
PORT_4_GLOBAL_SELECT:	equ 0h	;Port 4 global select register (PRT4GS)
PORT_4_DRIVE_0:			equ 0h	;Port 4 drive mode 0 register (PRT4DM0)
PORT_4_DRIVE_1:			equ ffh	;Port 4 drive mode 1 register (PRT4DM1)
PORT_4_DRIVE_2:			equ ffh	;Port 4 drive mode 2 register (PRT4DM2)
PORT_4_INTENABLE:		equ 0h	;Port 4 interrupt enable register (PRT4IE)
PORT_4_INTCTRL_0:		equ 0h	;Port 4 interrupt control 0 register (PRT4IC0)
PORT_4_INTCTRL_1:		equ 0h	;Port 4 interrupt control 1 register (PRT4IC1)
PORT_5_GLOBAL_SELECT:	equ 20h	;Port 5 global select register (PRT5GS)
PORT_5_DRIVE_0:			equ 20h	;Port 5 drive mode 0 register (PRT5DM0)
PORT_5_DRIVE_1:			equ ffh	;Port 5 drive mode 1 register (PRT5DM1)
PORT_5_DRIVE_2:			equ ffh	;Port 5 drive mode 2 register (PRT5DM2)
PORT_5_INTENABLE:		equ 0h	;Port 5 interrupt enable register (PRT5IE)
PORT_5_INTCTRL_0:		equ 0h	;Port 5 interrupt control 0 register (PRT5IC0)
PORT_5_INTCTRL_1:		equ 0h	;Port 5 interrupt control 1 register (PRT5IC1)
PORT_7_GLOBAL_SELECT:	equ 0h	;Port 7 global select register (PRT7GS)
PORT_7_DRIVE_0:			equ 0h	;Port 7 drive mode 0 register (PRT7DM0)
PORT_7_DRIVE_1:			equ 81h	;Port 7 drive mode 1 register (PRT7DM1)
PORT_7_DRIVE_2:			equ 81h	;Port 7 drive mode 2 register (PRT7DM2)
PORT_7_INTENABLE:		equ 0h	;Port 7 interrupt enable register (PRT7IE)
PORT_7_INTCTRL_0:		equ 0h	;Port 7 interrupt control 0 register (PRT7IC0)
PORT_7_INTCTRL_1:		equ 0h	;Port 7 interrupt control 1 register (PRT7IC1)

; end of file GlobalParams.inc
