/******************************************************************************
*  Generated by PSoC Designer ???
******************************************************************************/
#include <m8c.h>
// CSDCapacitor address and mask defines
#pragma	ioport	CSDCapacitor_Data_ADDR:	0x0
BYTE			CSDCapacitor_Data_ADDR;
#pragma	ioport	CSDCapacitor_DriveMode_0_ADDR:	0x100
BYTE			CSDCapacitor_DriveMode_0_ADDR;
#pragma	ioport	CSDCapacitor_DriveMode_1_ADDR:	0x101
BYTE			CSDCapacitor_DriveMode_1_ADDR;
#pragma	ioport	CSDCapacitor_DriveMode_2_ADDR:	0x3
BYTE			CSDCapacitor_DriveMode_2_ADDR;
#pragma	ioport	CSDCapacitor_GlobalSelect_ADDR:	0x2
BYTE			CSDCapacitor_GlobalSelect_ADDR;
#pragma	ioport	CSDCapacitor_IntCtrl_0_ADDR:	0x102
BYTE			CSDCapacitor_IntCtrl_0_ADDR;
#pragma	ioport	CSDCapacitor_IntCtrl_1_ADDR:	0x103
BYTE			CSDCapacitor_IntCtrl_1_ADDR;
#pragma	ioport	CSDCapacitor_IntEn_ADDR:	0x1
BYTE			CSDCapacitor_IntEn_ADDR;
#define CSDCapacitor_MASK 0x80
#pragma	ioport	CSDCapacitor_MUXBusCtrl_ADDR:	0x1d8
BYTE			CSDCapacitor_MUXBusCtrl_ADDR;
// CSDSW0 address and mask defines
#pragma	ioport	CSDSW0_Data_ADDR:	0x10
BYTE			CSDSW0_Data_ADDR;
#pragma	ioport	CSDSW0_DriveMode_0_ADDR:	0x110
BYTE			CSDSW0_DriveMode_0_ADDR;
#pragma	ioport	CSDSW0_DriveMode_1_ADDR:	0x111
BYTE			CSDSW0_DriveMode_1_ADDR;
#pragma	ioport	CSDSW0_DriveMode_2_ADDR:	0x13
BYTE			CSDSW0_DriveMode_2_ADDR;
#pragma	ioport	CSDSW0_GlobalSelect_ADDR:	0x12
BYTE			CSDSW0_GlobalSelect_ADDR;
#pragma	ioport	CSDSW0_IntCtrl_0_ADDR:	0x112
BYTE			CSDSW0_IntCtrl_0_ADDR;
#pragma	ioport	CSDSW0_IntCtrl_1_ADDR:	0x113
BYTE			CSDSW0_IntCtrl_1_ADDR;
#pragma	ioport	CSDSW0_IntEn_ADDR:	0x11
BYTE			CSDSW0_IntEn_ADDR;
#define CSDSW0_MASK 0x2
#pragma	ioport	CSDSW0_MUXBusCtrl_ADDR:	0x1ec
BYTE			CSDSW0_MUXBusCtrl_ADDR;
// CSDSW0 Shadow defines
//   CSDSW0_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSDSW0_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSDSW1 address and mask defines
#pragma	ioport	CSDSW1_Data_ADDR:	0x10
BYTE			CSDSW1_Data_ADDR;
#pragma	ioport	CSDSW1_DriveMode_0_ADDR:	0x110
BYTE			CSDSW1_DriveMode_0_ADDR;
#pragma	ioport	CSDSW1_DriveMode_1_ADDR:	0x111
BYTE			CSDSW1_DriveMode_1_ADDR;
#pragma	ioport	CSDSW1_DriveMode_2_ADDR:	0x13
BYTE			CSDSW1_DriveMode_2_ADDR;
#pragma	ioport	CSDSW1_GlobalSelect_ADDR:	0x12
BYTE			CSDSW1_GlobalSelect_ADDR;
#pragma	ioport	CSDSW1_IntCtrl_0_ADDR:	0x112
BYTE			CSDSW1_IntCtrl_0_ADDR;
#pragma	ioport	CSDSW1_IntCtrl_1_ADDR:	0x113
BYTE			CSDSW1_IntCtrl_1_ADDR;
#pragma	ioport	CSDSW1_IntEn_ADDR:	0x11
BYTE			CSDSW1_IntEn_ADDR;
#define CSDSW1_MASK 0x8
#pragma	ioport	CSDSW1_MUXBusCtrl_ADDR:	0x1ec
BYTE			CSDSW1_MUXBusCtrl_ADDR;
// CSDSW1 Shadow defines
//   CSDSW1_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSDSW1_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSDSW2 address and mask defines
#pragma	ioport	CSDSW2_Data_ADDR:	0x10
BYTE			CSDSW2_Data_ADDR;
#pragma	ioport	CSDSW2_DriveMode_0_ADDR:	0x110
BYTE			CSDSW2_DriveMode_0_ADDR;
#pragma	ioport	CSDSW2_DriveMode_1_ADDR:	0x111
BYTE			CSDSW2_DriveMode_1_ADDR;
#pragma	ioport	CSDSW2_DriveMode_2_ADDR:	0x13
BYTE			CSDSW2_DriveMode_2_ADDR;
#pragma	ioport	CSDSW2_GlobalSelect_ADDR:	0x12
BYTE			CSDSW2_GlobalSelect_ADDR;
#pragma	ioport	CSDSW2_IntCtrl_0_ADDR:	0x112
BYTE			CSDSW2_IntCtrl_0_ADDR;
#pragma	ioport	CSDSW2_IntCtrl_1_ADDR:	0x113
BYTE			CSDSW2_IntCtrl_1_ADDR;
#pragma	ioport	CSDSW2_IntEn_ADDR:	0x11
BYTE			CSDSW2_IntEn_ADDR;
#define CSDSW2_MASK 0x20
#pragma	ioport	CSDSW2_MUXBusCtrl_ADDR:	0x1ec
BYTE			CSDSW2_MUXBusCtrl_ADDR;
// CSDSW2 Shadow defines
//   CSDSW2_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSDSW2_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSDSW3 address and mask defines
#pragma	ioport	CSDSW3_Data_ADDR:	0x10
BYTE			CSDSW3_Data_ADDR;
#pragma	ioport	CSDSW3_DriveMode_0_ADDR:	0x110
BYTE			CSDSW3_DriveMode_0_ADDR;
#pragma	ioport	CSDSW3_DriveMode_1_ADDR:	0x111
BYTE			CSDSW3_DriveMode_1_ADDR;
#pragma	ioport	CSDSW3_DriveMode_2_ADDR:	0x13
BYTE			CSDSW3_DriveMode_2_ADDR;
#pragma	ioport	CSDSW3_GlobalSelect_ADDR:	0x12
BYTE			CSDSW3_GlobalSelect_ADDR;
#pragma	ioport	CSDSW3_IntCtrl_0_ADDR:	0x112
BYTE			CSDSW3_IntCtrl_0_ADDR;
#pragma	ioport	CSDSW3_IntCtrl_1_ADDR:	0x113
BYTE			CSDSW3_IntCtrl_1_ADDR;
#pragma	ioport	CSDSW3_IntEn_ADDR:	0x11
BYTE			CSDSW3_IntEn_ADDR;
#define CSDSW3_MASK 0x80
#pragma	ioport	CSDSW3_MUXBusCtrl_ADDR:	0x1ec
BYTE			CSDSW3_MUXBusCtrl_ADDR;
// CSDSW3 Shadow defines
//   CSDSW3_DataShadow define
extern BYTE Port_4_Data_SHADE;
#define CSDSW3_DataShadow (*(unsigned char*)&Port_4_Data_SHADE)
// CSDResistor address and mask defines
#pragma	ioport	CSDResistor_Data_ADDR:	0x14
BYTE			CSDResistor_Data_ADDR;
#pragma	ioport	CSDResistor_DriveMode_0_ADDR:	0x114
BYTE			CSDResistor_DriveMode_0_ADDR;
#pragma	ioport	CSDResistor_DriveMode_1_ADDR:	0x115
BYTE			CSDResistor_DriveMode_1_ADDR;
#pragma	ioport	CSDResistor_DriveMode_2_ADDR:	0x17
BYTE			CSDResistor_DriveMode_2_ADDR;
#pragma	ioport	CSDResistor_GlobalSelect_ADDR:	0x16
BYTE			CSDResistor_GlobalSelect_ADDR;
#pragma	ioport	CSDResistor_IntCtrl_0_ADDR:	0x116
BYTE			CSDResistor_IntCtrl_0_ADDR;
#pragma	ioport	CSDResistor_IntCtrl_1_ADDR:	0x117
BYTE			CSDResistor_IntCtrl_1_ADDR;
#pragma	ioport	CSDResistor_IntEn_ADDR:	0x17
BYTE			CSDResistor_IntEn_ADDR;
#define CSDResistor_MASK 0x20
#pragma	ioport	CSDResistor_MUXBusCtrl_ADDR:	0x1ed
BYTE			CSDResistor_MUXBusCtrl_ADDR;
